The present invention relates to a semiconductor device and its manufacturing technology, and particularly to a technique effective if applied to a semiconductor device having a power MISFET (Metal Insulator Semiconductor Field Effect Transistor).
A technique for causing a sense cell to divert a load current flowing through a power MISFET and detecting the load current flowing through the power MISFET by utilizing a voltage drop developed across a sense resistor coupled to the sense cell has been described in Japanese Unexamined Patent Publication No. He 3 (1991)-270274 (patent document 1). Described specifically, since an insulating film of a portion interposed between a gate insulating film of a power MISFET (main unit element) and a gate insulating film of a sense cell (sense or detection unit element) is formed thick, the density of each electrical charge accumulated in the surface of a semiconductor substrate located below the thick insulating film can be reduced as compared with the case in which an insulating film of the same thickness as the mutual gate insulating films is formed without forming the thick insulating film. As a result, the value of an accumulation layer resistor becomes large. Accordingly, the conduction between source layers at the power MISFET and the sense cell adjacent to each other can be ignored in an ON state of the power MISFET, and leak current can be reduced. That is, the leak current flowing via the accumulation layer resistor can be reduced. With the reduction in the leak current, the majority of current obtained by diverting the load current flows in a sense resistor pre-coupled between a source electrode of the power MISFET and a source region (sense electrode) of the sense cell as a sensed current. Namely, the accumulation layer resistor considered to be coupled in parallel to the sense resistor is increased, thereby making it possible to reduce the current flowing through the accumulation layer resistor and cause the majority of current to flow through the sense resistor. Thus, the sensed current becomes current proportional to the ratio between the number of cells in the power MISFET and the number of sense cells, and an error in the detection of the load current can be reduced.
A technique for reducing the dependence of an on-resistance ratio (current mirror ratio) on a gate voltage and a channel temperature thereby to enhance current detection accuracy in a semiconductor device equipped with a current detection or sense terminal has been described in Japanese Unexamined Patent Publication No. Hei 11 (1999)-345965 (patent document 2). Described specifically, a first semiconductor element and a second semiconductor element that share a drain terminal are formed within the same semiconductor substrate. The source of the first semiconductor element is used as a source terminal and the source of the second semiconductor element is used as a mirror terminal for current detection. At this time, a source diffusion layer formed in a cell for the second semiconductor element is formed only at a portion where it is mutually opposed to a source diffusion layer of an adjoining cell. Alternatively, each cell unformed with some or all of the source diffusion layer is formed in a location other than the outermost peripheral cell of the first semiconductor element. Or a resistor comprised of a semiconductor is coupled between the source of the second semiconductor element and the mirror terminal. With the provision of such a configuration, on-resistance component configurations of the first and second semiconductor elements approach each other, and the dependence of the on-resistance ratio (current mirror ratio) on the gate voltage and the channel temperature can be reduced.
A technique for providing a trench gate type semiconductor device that is equipped with a high-precision current sense function and has achieved an increase in breakdown voltage, has been described in Japanese Unexamined Patent Publication No. 2006-93459 (patent document 3). Described specifically, the semiconductor device is equipped with a main cell and a sense cell. The main cell and the sense cell are separated from each other by each separation area. The main cell and the sense cell that configure the semiconductor device take such a structure that the breakdown voltage is supported by a PN junction based on a P floating region and an N− drift region formed in a lower portion of each gate trench with a gate electrode embedded therein in addition to a PN junction based on an N− drift region and a P− body region formed in a semiconductor substrate. A breakdown voltage holding structure equivalent to the main cell and the sense cell has been adopted even in the separation area. Described specifically, a gate trench with a gate electrode built therein is formed even in its corresponding separation area, and a P floating region is formed in a lower portion of the gate trench. Thus, the separation area is also brought to the structure equivalent to the main and sense cells, thereby making it possible to suppress a reduction in the breakdown voltage. Further, providing each gate trench and the P floating region formed in the lower portion of the gate trench in the separation area makes it possible to suppress current flowing into the sense cell. Thus, according to this technique, a trench gate type semiconductor device can be realized which is equipped with a high-precision current sense function and has achieved an increase in breakdown voltage.